1. Filed of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to a method of making insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in the channel in order to modulate the longitudinal conductance of the channel.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, and the polysilicon is anisotropically etched to provide the gate. Thereafter, the gate provides an implant mask during the implantation of source and drain regions, and the implanted dopants are driven-in and activated using a high-temperature anneal that would otherwise melt the aluminum.
Photolithography is frequently used to create patterns that define where the polysilicon layer is etched. Typically, the wafer is cleaned and prebaked to drive off moisture and promote adhesion, an adhesion promoter is deposited on the wafer, a few milliliters of positive photoresist are deposited onto the spinning wafer to provide a uniform layer, the photoresist is soft baked to drive off excess solvents, the photoresist is irradiated with an image pattern that renders selected portions of the photoresist soluble, a developer removes the irradiated portions of the photoresist, an optional de-scum removes very small quantities of photoresist in unwanted areas, the photoresist is hard baked to remove residual solvents and improve adhesion and etch resistance, the etch is applied using the photoresist as an etch mask, and the photoresist is stripped. Therefore, the photoresist has the primary functions of replicating the image pattern and protecting the underlying polysilicon when etching occurs.
In general, the term "resolution" describes the ability of an optical system to distinguish closely spaced objects. The minimum resolution of a photolithographic system is the dimension of minimum linewidth or space that the machine can adequately print or resolve. While optical photolithography continues to be the dominant technology in semiconductor manufacturing because it is well established and is capable of implementing sub-micron resolution at least as low as 0.35 microns using current equipment, as feature sizes approach 0.5 microns and below, and these features extend across wafer areas of a square inch and more, extensive efforts are being directed at developing alternative technologies. Electron-beam and X-ray technologies have demonstrated patterning capabilities that extend beyond the limits of optical systems. However, these alternative approaches have certain drawbacks. For instance, electron-beam lithography has low throughput that lags far behind the requirements of industrial applications, and X-ray lithography has very high investment costs associated with synchrotron radiation sources as well as problems with mask accuracy, alignment, and wafer distortion.
Thus, workers in the art recognize that there are obvious incentives for trying to push the currently dominant technology (optical photolithography) into the fine-line region. Such an effort, if successful, has the potential for significantly better patterning capabilities, which in turn reduces the dimensions of the devices.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to spacers adjacent to the gate. The spacers are typically oxides or nitrides. The purpose of the lighter dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The heavier dose forms a low resistivity heavily doped region of the drain. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics. A known fabrication sequence includes forming lightly doped source/drain regions, forming the spacers, and then forming heavily doped source/drain regions. Another known fabrication sequence includes forming disposable spacers, forming heavily doped source/drain regions, removing the disposable spacers, and then forming lightly doped source/drain regions (between the heavily doped source/drain regions and the gate).
Disadvantages of LDDs include increased fabrication complexity and increased parasitic resistance due to their light doping levels. During operation, LDD parasitic resistance decreases drain current. Linear drain current (in the linear or triode region) is reduced by the parasitic resistance in both the source and drain. Saturation drain current (in the saturation region) is largely unaffected by the parasitic resistance of the drain but greatly reduced by the parasitic resistance of the source. Therefore, saturation drain current can be improved while reducing hot carrier effects by providing a lightly doped region only on the drain side. That is, the drain includes lightly and heavily doped regions, and the entire source is heavily doped.
Asymmetrical IGFETs (with asymmetrically doped sources and drains) are known in the art. For instance, U.S. Pat. No. 5,424,229 entitled "Method For Manufacturing MOSFET Having An LDD Structure" by Oyamatsu discloses providing a mask with an opening over a substrate, implanting a dopant through the opening at an angle to the substrate to form a lightly doped drain region on one side without a corresponding source region on the other side, forming a gate in the opening which overlaps the lightly doped drain region, removing the mask, and implanting heavily doped source and drain regions using the gate as an implant mask. As another example, U.S. Pat. No. 5,286,664 entitled "Method For Fabricating The LDD-MOSFET" by Horiuchi discloses forming a gate, implanting lightly doped source and drain regions using the gate as an implant mask, forming a photoresist layer that covers the source side and exposes the drain side, forming a single spacer on the drain side using liquid phase deposition (LPD) of silicon dioxide, stripping the photoresist, and implanting heavily doped source and drain regions using the gate and single spacer as an implant mask.
A drawback to conventional asymmetrical IGFETs is that typically the heavily doped source and drain regions are the most heavily doped regions of the source and drain and have identical dopant concentrations. Although the doping concentration of the heavily doped drain region may be constrained in order to reduce hot carrier effects, the doping concentration of the heavily doped source region need not be constrained in this manner. Furthermore, increasing the doping concentration of the heavily doped source region reduces source-drain series resistance, thereby improving drive current.
Providing low resistance contacts for the gate, source and drain can be accomplished using refractory metal silicide. In one approach, a thin layer of refractory metal is deposited over the structure after forming the lightly and heavily doped source/drain regions and the spacers, and heat is applied to form silicide contacts wherever the refractory metal is adjacent to silicon (including single crystal silicon and polysilicon). Thereafter, an etch is applied that removes unreacted refractory metal over the spacers to prevent bridging silicide contacts for the gate, source and drain. Various silicides such as titanium silicide (TiSi.sub.2), tungsten silicide (WSi.sub.2), molybdenum silicide (MoSi.sub.2), cobalt silicide (CoSi.sub.2) and tantalum silicide (TaSi.sub.2) have been used for this purpose. For instance, the sheet resistance of titanium silicide is as low as 3 to 6 .OMEGA./sq, whereas heavily doped polysilicon exhibits a sheet resistance on the order of 15 to 30 .OMEGA./sq. Another advantage to this approach is that the silicide contacts for the gate, source and drain are formed simultaneously and are self-aligned by the spacers. This self-aligned silicide is sometimes referred to as "salicide."
In complex integrated circuits, several hundred thousand or millions of active devices (transistors, capacitors, diodes, resistors, etc.) are fabricated on a single monolithic substrate, and an interconnect structure includes patterned conductive lines for interconnecting the active devices according to a specific circuit function. Typically, the active devices are formed in active regions of the substrate, and the active regions are separated by field regions of the substrate. IGFETs are generally self-isolated provided the source and drain are reverse-biased with respect to the substrate. However, field dielectrics are usually formed on the field regions to prevent the refractory metal from reacting with the field region, thereby avoiding silicide bridges between active regions. Furthermore, field dielectrics are usually thick enough to prevent overlying conductive lines from forming channels in the field regions, thereby avoiding parasitic devices in the field regions. Field dielectrics are often on the order of 2000 to 5000 angstroms thick.
LOCOS is a well-known technique for providing field dielectrics. LOCOS includes forming a pad oxide over the substrate, forming a nitride layer over the pad oxide, etching the nitride layer over the field regions, and thermally growing the pad oxide over the field regions. LOCOS can be carried out using many different process flows, including semi-recessed or fully-recessed techniques. However, LOCOS can cause problems. For instance, bird's beak encroachment can cause submicron active regions to virtually disappear unless rework is done. Oxidation-enhanced diffusion can cause perpendicular segregation of shallow channel-stop implants such as boron. In addition, Kooi ribbons of silicon nitride can form on the active region due to the reaction of NH.sub.3 (which diffuses through the pad oxide) and the silicon surface. Since Kooi ribbons degrade gate oxide quality, often a sacrificial oxide must be formed and stripped to remove the ribbons before growing the gate oxide.
U.S. Pat. No. 5,643,825 entitled "Integrated Circuit Isolation Process" by Gardner et al. discloses a promising alternative to LOCOS. The improved process utilizes a blanket formation of first and second dielectrics across an entire semiconductor substrate. In a subsequent step, the first and second dielectrics are removed in areas overlying the active regions. The resulting field dielectric structure is relatively thin, yet demonstrates superior dielectric properties.
Based on the foregoing, a need exists for an improved method of making an IGFET and a field dielectric between active regions, particularly where the IGFET is an asymmetrical device with low source-drain resistance, an LDD and an extremely narrow gate, silicide contacts are formed on the gate, source and drain, the field dielectric substantially eliminates encroachment and other problems associated with LOCOS, and relatively few processing steps are required.